Semiconductor memory
US7113441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2005 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Feb 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.