Method of address distribution time reduction for high speed memory macro
US7113443B2 · kind B2 · utility
3Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Oct 14, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.