Method and system for varying an echo canceller filter length based on data rate
US7113491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Oct 30, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides methods and systems for providing efficient use of available CPU cycles that may be achieved by reducing the length of the echo canceller filter. An echo canceller's adaptive algorithm may be implemented to reach a lower mean squared error due to the increased training time allowed by cycle reduction. Total power consumption of a processor may be reduced by reducing the number of multiplications (and/or other operations) that may be performed by an echo canceller filter for each time iteration. This may be achieved by not performing multiplications on taps that are not being used. For higher rates, a shorter echo canceller filter may be implemented by transmitting less energy in low frequencies. As a result, the temporal length of the echo channel may be shortened thereby reducing the total number of taps needed to model the channel. The present invention may further enhance performance by reducing CPU cycles and allowing for more echo canceller training time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.