Semiconductor memory having test function for refresh operation
US7114025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Jul 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.