Structure and method of cache memory data update
US7114031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Apr 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a structure and a method of data update in a cache memory inside a local processor, which uses the feature of cache control. A buffer block of a header buffer is mapped to a memory space at several different address sectors addressed by the local processor. Whenever the local processor attempts to access the internal cache memory, cache missing will occur so that a local processor will be forced to alternatively request new data from buffer blocks of a header buffer in a HCA. Consequently, the whole block is loaded into cache memory. This does not only boost cache update performance but also accelerates packet access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.