Generic architecture and system for a programmable serial port having a shift register and state machine therein
US7114093B2 · kind B2 · utility
11Cited by
4References
65Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | May 7, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed programmable serial port having a finite state machine, a clock generator capable of controlling shifting of bits from a shift register and a shift register having a bit counter capable of maintaining a numbered count of data bits in a serial output. The clock generator and shift register reduce the burdens on a finite state machine, thus improving data throughput and the ability to provided data according to a multitude of data protocols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.