Method for VLSI system debug and timing analysis
US7114136B2 · kind B2 · utility
9Cited by
5References
45Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 16, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Dec 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes a method such as, but not limited to, time resolved photon emission to observe transistor level switching activity in an integrated circuit (IC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.