Standard cell back bias architecture

US7115460B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Ching-Hao Shaw · Plano, US
• Chih-Hung Wu · Taoyuan, TW
• Charlie Chueh · Baoshan, TW

Key dates

• Filing date: Aug 20, 2004
• Grant date: Oct 3, 2006
• Expiry date: Aug 28, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/907

Abstract

An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.