Systems and methods for sense FET calibration
US7116113B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2005 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | May 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R15/146
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems, methods and circuits for sense circuit calibration. In one particular case, a system is provided that includes a sense circuit, a calibration circuit, and a sample and hold circuit. The sense circuit provides a sense current that is derived from either a reference current or a load current depending upon the operational state. The calibration circuit includes a calibration amplifier electrically coupled to the reference current and to the sense current. The calibration amplifier outputs a calibration signal representing a difference between the reference current and the sense current. The sample and hold circuit is operable to store a value representative of the calibration signal, and useful in forming a calibration offset current applied to the sense current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.