Method and apparatus for effectively re-downloading data to a field programmable gate array
US7116130B2 · kind B2 · utility
2Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Oct 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit, such that according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.