Method and system for reducing power consumption in digital circuitry using charge redistribution circuits
US7116137B2 · kind B2 · utility
6Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Jan 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing power consumption in digital circuits using charge redistribution include a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each signal line that isolates the signal line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state.This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.