Digital circuit tolerant of race condition problem
US7116152B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2005 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Jan 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/66
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital circuit tolerant of a race condition problem circuit includes a sense amplifier receiving first and second input data and generating first and second sense amplification signals in response to an enable clock signal generated using a clock signal and an enable signal, and a cascode signal latch receiving the first and second sense amplification signals and generating first and second cascode signals. The first and second sense amplification signals or the first and second cascode signals are selectively transmitted by a switch unit as first and second output control signals, respectively, and then output as first and second multiplexer output signals, respectively, by a dynamic multiplexer in response to a predetermined selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.