Buffer circuit
US7116163B2 · kind B2 · utility
3Cited by
8References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Sep 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45475
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit comprised of two matched stages is provided. The first stage develops a replica voltage that is used in the second stage as the input to a wide-band amplifier. The combination of the two feedback loops in the circuit result in improved linearity. The first amplifier dominates for moderate frequencies while the second amplifier takes over for high frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.