Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device
US7116581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2005 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Apr 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array includes a plurality of memory cells each of which has a control gate and a floating gate. A programming circuit operates in a first programming mode followed by a second programming mode. In the first programming mode, the programming circuit applies a first program pulse to first memory cells while progressively increasing a programming capability of the first program pulse until threshold voltages of the first memory cells become higher than or equal to a first reference voltage. In the second programming mode, the programming circuit applies a second program pulse to second memory cells included in the first memory cells and having threshold voltages lower than a second reference voltage that is higher than the first reference voltage until the threshold voltages of the second memory cells become higher than or equal to the second reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.