Digital decimation filter having finite impulse response (FIR) decimation stages
US7117235B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2002 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Jul 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0671
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital decimation filter having Finite Impulse Response (FIR) decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital intermediate frequency (IF) stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.