Mitigating access penalty of a semiconductor nonvolatile memory
US7117306B2 · kind B2 · utility
9Cited by
20References
34Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 19, 2002 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Jan 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Adding a nonvolatile storage (e.g., a cache) to an associated memory array within a semiconductor nonvolatile memory may mitigate the access penalty that occurs in semiconductor nonvolatile memories, such as flash memories and flash devices. For example, in response to a memory access request, the cache may be accessed for data before accessing the memory array and the data may be selectively stored from the memory array into the cache. In another embodiment, an asynchronous access to a semiconductor nonvolatile memory may be converted into a synchronous access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.