Debug port disable mechanism
US7117352B1 · kind B1 · utility
49Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.