Timing method and apparatus for digital logic circuits
US7117384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2003 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Nov 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG04F10/04
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A differentiated granularity timing apparatus and a method to provide various flexible timing granularities without requiring much memory space and complex circuit design are disclosed. The differentiated granularity timing apparatus of the present invention comprises a differentiated granularity timing unit, a comparing unit, an adder and a buffer. The buffer is for storing a time value. The comparing unit further comprises a comparator and a plurality of predetermined time interval values stored therein. The comparator is for outputting a control signal according to the time value. The differentiated granularity timing unit further comprises a multiplexer and a plurality of timers. Each timer is for providing a timing signal with different timing granularities respectively. The multiplexer is for outputting one of the timing signals with the corresponding timing granularity according to the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.