Memory device with data line steering and bitline redundancy
US7117400B2 · kind B2 · utility
3Cited by
11References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2002 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Oct 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.