Decoder architecture for reed solomon codes
US7117425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2002 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Nov 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/158
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Reed Solomon decoder architecture that uses a modified version of the error-evaluator polynomial form having a significantly reduced area of the dominant PDU unit, without loss in iteration time, in slice circuitry, which rotates terms to share a common multiplier and other circuitry. In addition, a B polynomial is stored, and associated overflow flags are implemented, to allow its storage to be minimized using a dual-multiplier arrangement. The decoder for error correcting codes comprises a syndrome calculation circuit, and a polynomial determining unit comprising slices, and a single multiplier in each of the slices, wherein each of the slices is employed a plurality of times in successive clock cycles. A correction circuit comprises a first multiplier employed when a scratch polynomial has overflowed, and a second multiplier employed when not overflowed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.