Determining feasibility of IC edits
US7117476B2 · kind B2 · utility
3Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | May 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer method of analyzing an integrated circuit (“IC”) masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.