Method of fabricating an electronic package having underfill standoff
US7118940B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Aug 5, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package having a controlled standoff height between a surface mount device and a circuit board. The electronic package includes a circuit board having a substrate and circuitry including mounting pads and a surface mount device having circuitry and contact terminals. Solder joints connect the contact terminals of the surface mount device to the mounting pads on the circuit board. A dielectric underfill is disposed between the circuit board and the surface mount device, and a plurality of standoff members are disposed in the underfill material to provide a separation distance between the circuit board and the surface mount device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.