Quad flat non-leaded package comprising a semiconductor device
US7119421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2003 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Jun 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is proposed. The semiconductor package includes a discrete semiconductor chip on a die pad, a plurality of bond pads situated next to the chip and formed with a plurality of connecting mechanisms and an encapsulant for encapsulating the chip and the pads. In a preferred embodiment the die pad and/or the bond pads comprise means for vertically and laterally interlocking the pads to the encapsulant. The interlocking means of the bond pads and the die pad significantly enhance the bonding strength between the pads and the encapsulant for preventing delamination or cracking, so that quality and reliability of the quad flat non-leaded semiconductor package comprising a discrete can be assured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.