Packaging for enhanced thermal and structural performance of electronic chip modules
US7119433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Jun 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an integrated circuit packaging structure, such as in a SCM, DCM, or MCM, a method and apparatus for increasing heat spreader size and thus thermal performance is disclosed. The packaging structure includes a first substrate; an electronic device operably coupled to a top surface defining the first substrate; a heat spreader having a first surface operably coupled to a top surface defining the electronic device and an opposite second surface in thermal communication with a second substrate; and a frame defining an opening therethrough. The frame is further defined by an inwardly extending ledge configured to allow the heat spreader to extend at least to a peripheral edge defining a perimeter of the first substrate. In an exemplary embodiment, the second substrate includes one of a heat sink, cooling plate, thermal spreader, heat pipe, thermal hat, package lid, or other cooling member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.