Signal samplers and buffers with enhanced linearity
US7119584B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Dec 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention recognizes that sampler linearity is degraded because transfer voltage across a sampler's buffer varies with amplitude of the analog signal being sampled. Because this transfer voltage is in the signal path it modulates the signal and distorts the resulting sample. In the invention, sampler embodiments are provided which include replica current generators that provide and route sample currents to sample capacitors so that an associated buffer transistor can transfer a faithful copy of the analog signal's potential to the sample capacitor and thereby significantly enhance the sampler's linearity. The replica current generators generally include a replica load that mimics the sample load driven by the buffer transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.