High frequency divider state correction circuit
US7119587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | May 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/58
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.