Electronic tampering detection system
US7119684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2005 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Apr 25, 2025 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB65D2401/00
- WIPO fieldHandling
- WIPO sectorMechanical engineering
Abstract
An electronic tampering detection system is applied to a blank which can be formed into a package through the use of closure tabs which are coated with an electrically conductive adhesive. An electronic chip or CPU is applied to the blank and electrically conductive traces are printed or otherwise formed on the blank to connect the CPU to a first pair of the closure tabs to form an electric circuit. Other traces on the blank connect the first pair of closure tabs to the other closure tabs to form an enlarged circuit. The CPU has procedure memory, data memory, a power source, a clock and communication means associated therewith. If a package is opened accidentally or intentionally before it should be opened by way of the closure tabs the electric circuit is broken and a time stamp from the CPU clock is stored in the data memory for later retrieval. The circuit can be formed as resistances in parallel and an analog to digital converter can be used to provide an appropriate signal to the CPU. The electric circuit can cover a large portion of the blank's surface to provide a signal in the event of unauthorized penetration of the formed package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.