Method for aligning capacitor plates in a security tag and a capacitor formed thereby
US7119685B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Jun 4, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit element the presence of the circuit element includes first and second capacitor plates disposed over the surface of the substrate in an aligned relationship with each other. The aligned relationship has manufacturing variations in the relative positioning of the first and second capacitor plates and a dielectric layer disposed between the first and second capacitor plates. At least one of the first and second capacitor plates is formed substantially smaller relative to the other of the first and second capacitor plates. The at least one of the capacitor plates is disposed at a predetermined offset in at least one planar direction from an edge of the other of the first and second capacitor plates. The predetermined offset is selected according to the manufacturing variations to prevent variations in the value of capacitance of the capacitor due to the manufacturing variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.