Error feedback structure for delta-sigma modulators with improved stability
US7119726B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Oct 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/436
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to α* (maximum value of input signal), α>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<α<2.0, more preferably 1.4<α<1.6. The filter has a transfer function of H1(z)=2z−1−z−2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.