Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions
US7120053B2 · kind B2 · utility
16Cited by
16References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2005 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Jan 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.