Inter-procedural allocation of stacked registers for a processor
US7120775B2 · kind B2 · utility
6Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2003 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.