System and method for reading and writing a thread state in a multithreaded central processing unit
US7120783B2 · kind B2 · utility
25Cited by
35References
4Claims
0Family size
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Key dates
| Filing date | Jun 22, 2001 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Oct 7, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.