Semiconductor device
US7122901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2005 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Apr 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09781
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device, a plurality of wiring layers each patterned in a required shape are laminated over both surfaces of an insulating base material with insulating layers interposed therebetween, and electrically connected to one another through via holes piercing the insulating layers in the direction of thickness. A chip is mounted in an embedded manner in one insulating layer over at least one surface of the insulating base material. Electrodes of the chip are connected to one wiring layer. Through holes are formed in portions of the insulating base material, the portions corresponding to a mount area for the chip. Via holes are formed on outwardly extending portions (pad portions) of the wiring layer connected to a conductor layer formed at least on the inner walls of the through holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.