Core logic chip conducting multi-channel data transmission
US7123267B2 · kind B2 · utility
0Cited by
2References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 29, 2003 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jul 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An additional data transmission channel is provided between the north bridge chip and the system memory when the graphic accelerator is integrated into the north bridge chip. The additional data transmission channel can be similar to the existent data transmission channel between the north bridge chip and the system memory for providing extensive data transmission bandwidth. Alternatively, the additional data transmission channel can be specific to the communication between the graphic accelerator in the north bridge chip and the frame buffer in the system memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.