Clock jitter limiting scheme in video transmission through multiple stages
US7123307B1 · kind B1 · utility
6Cited by
17References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2001 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Apr 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4347
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scheme to reduce clock jitter is disclosed in applications where video content is transmitted through multiple stages, each having a switch allowing that stage's video stream to be selected. The video data is re-clocked using a new clock at each stage. Before re-clocked, the video data from the preceding stage is scaled into a constant resolution using a digital scaler. Since the downstream stages could re-clock the video as if it were sent at the same frequency, there is no need to anticipate the changeable video frequency and to create the necessary low-jitter clock in programmable logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.