Thin-film transistor with set trap level densities, and method of manufactures
US7123314B2 · kind B2 · utility
4Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jul 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A light shielding film capable of shielding against light entering an active layer of a TFT and electroconductive is formed on the lower layer side of the active layer. Electrical stress is applied by causing a current in an insulating film between source and drain electrodes and the light shielding film to introduce a trap level at a density at least about 5×1012/cm2 into a source region and a drain region in a surface portion of the active layer on the light shielding film side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.