Memory module and memory system
US7123497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jan 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. In this constitution, a wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.