Reducing latency and power in asynchronous data transfers
US7123674B2 · kind B2 · utility
4Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Aug 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable signal operates to enable a source register to capture data from a source domain. The source-enable signal may be controlled by a source-inhibit signal. The source-inhibit signal prevents the synchronous-pulse signal from producing the source enable signal and capture clock until data is available for transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.