Clock, data and time recovery using bit-resolved timing registers
US7123675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2002 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Oct 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.