Latching electronic circuit for random number generation
US7124155B2 · kind B2 · utility
8Cited by
9References
8Claims
0Family size
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Key dates
| Filing date | Jul 25, 2002 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Feb 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A physical random number generator has a bi-stable latch that operates to generate a random number bit in response to a reception of one or more voltage input signals and a clock signal. A voltage source provides the voltage input signal(s) for provoking the bi-stable latch into a metastable state. A clock provides the clock signal for triggering the bi-stable latch. When triggered, the bi-stable latch latches the random number bit as a function of its metastable state provoked by the voltage input signal(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.