Programmable interface link layer device
US7124227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2002 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Dec 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/4608
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interface link layer device is connected in-between a first sub network and a long delay link to which at least one second sub network is connected. The interface link layer device comprises at least two storage areas, whereby new configuration data received via the long delay link is written to one of the storages to simulate the devices of the second network within the first network. In case a self ID phase is initiated as long as the configuration information is not complete yet, the respective other storage area is accessed. In case a self ID phase is initiated as soon as or after the new configuration data is complete, the storage area to which the new configuration data has been written is used for setting up the self ID packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.