Apparatus and methodology for a write hub that supports high speed and low speed data rates
US7124241B1 · kind B1 · utility
7Cited by
2References
85Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2003 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jan 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9021
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A write hub is described. The write hub has a plurality of registers. Each one of the registers helps generate a write address to a different memory bank from amongst a plurality of memory banks. Each of the registers are arranged in a ring so that each register can pass a pointer value toward a next register within the ring. The ring of registers further comprise a multiplexer between each of the registers. Each multiplexer has an output path that flows toward a next register within the ring relative to the multiplexer. Each multiplexer can introduce a pointer value to the ring at a next register within the ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.