Method and apparatus for translating guest physical addresses in a virtual machine environment
US7124273B2 · kind B2 · utility
11Cited by
45References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2002 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Nov 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus are used to efficiently translate memory addresses. The translation scheme yields a translated address, a memory type for the translated address, and a fault bit for the translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.