Security chip architecture and implementations for cryptography acceleration
US7124296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2005 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Sep 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/123
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An architecture and a method for cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed size “cells.” The fixed-size cells are then processed and reassembled into packets. The cell-based packet processing architeture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet or control parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.