Generating a split power plane of a multi-layer printed circuit board
US7124390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2003 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Nov 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09663
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses generate a split power plane for a multiplayer printed circuit board (PCB). An aspect of the invention supports the generation of a split power plane by constructing wireframes corresponding to each of the power voltages. If a crossover between different voltage wireframes exists, at least one of the voltage wireframes may be modified in order to eliminate the crossover. With another aspect of the invention, a trace layout, corresponding to the wireframe, is constructed in accordance with electrical current requirements, e.g. average electrical current and peak electrical current, of the associated components. With another aspect of the invention, a plane that contain the traces that associated with a power voltage may be enhanced by increasing the associated area of the layout in accordance with the available area of the split power plane. The enhancement of a plane may be prioritized in accordance with peak electrical current that is associated with the plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.