Large area electronic device with high and low resolution patterned film features
US7125495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Mar 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/60
Abstract
Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes. Redundant structures are formed to further improve tolerance to misalignment, with non-optimally positioned structures removed (etched) during formation of the low resolution interconnect structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.