Peak detection circuit with double peak detection stages
US7126384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/04
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first period, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second period longer than the first period, and outputs a digital peak signal. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.