System for clock duty cycle stabilization
US7126396B1 · kind B1 · utility
12Cited by
4References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 16, 2003 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Jul 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal duty cycle stabilization system. The system includes a clock signal duty cycle stabilization circuit having an edge detection circuit and a latch circuit. The edge detection circuit is configured to receive an external clock signal and generate an output therefrom. The latch circuit is coupled to receive the output from the edge detection circuit. The latch circuit is configured to produce a rising edge of an internal clock signal and a falling edge of the internal clock signal in accordance with the output of the edge detection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.