Method and an apparatus to generate static logic level output
US7126398B1 · kind B1 · utility
0Cited by
31References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Feb 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.