Digital phase locked loop with selectable normal or fast-locking capability
US7126429B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Sep 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase locked loop with fast locking capability includes a digitally controlled oscillator for producing an output signal phase locked to an input reference clock, a phase detector for measuring the phase difference between said input reference clock and a feedback clock, and a loop filter for producing a control signal for the digitally controlled oscillator The loop filter includes a proportional circuit for developing a first signal proportional to said phase difference, an integrator for developing a second integrated signal from said first signal, an adder for adding said first and second signals to develop said control signal, and a weighting circuit, preferably a linear multiplier, for selectively adding extra weight to the first signal at an input to the integrator to shorten the locking time of the phase locked loop in a fast locking mode and to rapidly achieve a stable frequency in holdover mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.